The primary channel’s UART translates the bit-by-bit data on the serial cable into bytes of data that can be interpreted by the QED-Forth Kernel or by your application program. Any required SPI output signals must be configured as outputs by setting the appropriate bits in the Port D data direction register which is named PORTD.DIRECTION in the QED-Forth kernel. Setting the MSTR bit initializes the 68HC11 as a master, and clearing the MSTR bit initializes it as a slave. Initializing the 68HC11 as a slave (by clearing the MSTR bit in the SPCR control register as explained below) automatically configures the /SS pin as an input. Regardless of the network, however, there are only four signals used: SCK provides a synchronized clock, MOSI and MISO signals are used for data transmission and reception, and /SS configures the 68HC11 as a master or slave device. The advantage of such a multi-drop RS-232 network is that the communications are full duplex, with each communicating party capable of simultaneous transmission and reception of data. Unlike the standard RS232 protocol, RS485 allows many communicating parties to share the same 3-wire communications cable. In each case, your QVGA Controller will be communicating at 19200 baud, and this baud rate will remain in effect until another BAUD1.AT.STARTUP command is executed, or until you invoke the Special Cleanup Mode as described earlier.

This allows standard point-to-point full duplex communications, as well as a multi-drop configuration with one master (a single QVGA Controller or a desktop computer) and multiple QVGA Controller slaves. For RS232 operation: Install the jumper shunt across the two pins closest to the crystal (the default configuration). Hardware is interfaced to the SPI via four PORTD pins named /SS, SCK, MOSI, and MISO brought out to pins 11 through 14 on the Digital I/O connector (see Appendix A). Move the serial cable from the "Serial Port 1" connector to the "Serial Port 2" connector at the QVGA Controller. If you have not yet compiled the GETSTART program and you want to do the exercises here, open GETSTART.C in your TextPad editor, click on the Make Tool (the Make icon), and after the compilation is done, enter the Terminal Program by clicking on the terminal icon and use the "Send Text File" menu item to send GETSTART.DLF to the QVGA Controller. Now select the "Communications" item in the "Settings" menu of the Terminal program, and click on 1200 baud (or whatever baud rate you selected in the command above). By connecting pairs of these handshaking signals together, what is rs485 cable the terminal or PC can be made to think that the QVGA Controller is always ready to send and receive data.

These signals may alternatively be redirected to the digital inputs and outputs used by the second serial port if hardware handshaking is required. Many terminals and PCs, however, do rely on hardware handshaking to determine when the other party (in this case the QVGA Controller) is ready to accept data. Thus in Table 11 5 , RTS1 is connected to CTS1, and DSR1 is connected to DTR1 onboard the QVGA Controller using zero ohm shorting resistors. Care must be taken when using A/B naming. The SPI control register, SPCR, contains 8 bits which must be initialized for proper control of the QVGA Controller’s SPI (M68HC11 Reference Manual, p.8-7). Given a properly wired network and a properly configured SPCR control register, a master device may transmit a message by simply storing the byte to the SPDR data register. After a data transfer is initiated by writing to the SPDR data register, the processor may poll the SPSR status register until the SPIF flag is set. The WCOL flag is set when a write collision occurs. A mode fault occurs when the SPI senses that a multimaster conflict (MC68HC11F1 Technical Data Manual, p.10-5) exists on the network as explained above in connection with the /SS input.

In this situation, if the /SS input is pulled low while the 68HC11 is the master, the processor detects a "mode fault" (by setting a bit in the SPI status register) meaning that there is more than one master device on the SPI bus. When this bit is high, the transceiver is in transmit mode. If the CPHA bit is 1, the /SS line may be tied low between successive transfers. The /SS (active-low slave select) signal enables data transfers by slave devices when it is active low. Remember that the /SS is active low so to select a device you need to set the pin low; otherwise the pin should idle high. If the 68HC11 is initialized as a master (by setting the MSTR bit in the SPCR control register as explained below) then bit 5 of the Port D data direction register (DDRD) determines whether /SS is an input or an output. If bit 5 of DDRD is 0, then /SS is an input. If the /SS pin of the master is an output, it can be controlled independently of the SPI system.